Peripheral Component Interconnect Express (PCIe) is a high-speed serial interconnect bus standard, as established by the PCI SIG (PCI Special Interest Group). The PCIe bus can be used in computer hardware as a motherboard-level interconnect or as an expansion card interface. A motherboard-level interconnect links together motherboard mounted peripherals, while an expansion card interface is used by peripherals (e.g., a video card) that fit into the motherboard's expansion slots. In one embodiment, as illustrated in FIG. 1, an upstream port or rootport 102 is connected to a downstream port or endpoint 104.
PCIe Generation 3.0 (PCIe Gen3) is the latest PCIe standard with increased interconnect link speeds, but with accompanying increased link equalization training time requirements. PCIe link equalization training is the process whereby a connected rootport 102 and endpoint 104 select parameters that ensure a favorable bus bit error rate (BER) when transmitting and receiving traffic over the PCIe interconnect link at higher speeds. The challenge with existing PCIe link equalization training processes is that under normal circumstances such equalization training can be very lengthy (e.g. 100 ms). During such a training interval, the bus being unavailable, data will not be transmitted across the bus. Attempts to send data during such link equalization training times will either fail with a completion timeout (e.g. returning OxFF's) or be held-off within the sending PCIe device 102, 104 until the training is complete.
In many system designs a peripheral or mezzanine bus may be a critical component for system operation, hence a long period of unavailability may compromise operating system robustness, or result in the loss of data. For example, a common rule of thumb for system BIOS code inside a System Management Mode (SMM) handler is never to exceed 0.5 ms delay, however if such code was to access a PCIe device during a retraining (re-equalization) and thus be held up for 0.5 ms or longer, the operating system software would trigger an error message, or lock-up, or can lead to data corruption or a system crash.
One solution is to attempt to constrain equalization training sequences to system boot times (e.g. before the operating system loads). However, should the original link be lost and a new link established with new parameters required, an equalization training sequence or training arc will be required to be performed outside of the initial boot sequence. As discussed in detail below, equalization training may be desired or required when electrical characteristics of a PCIe Gen3 link change during run-time and a link that was previously working has degraded to the point where data loss is not recoverable, or when the bit error rate (BER) exceeds a tolerable threshold. Such out of initial boot sequence equalization retraining can result in problems for devices connected to the effected PCIe link that are sensitive to the quantity of down-time required for equalization training or retraining. While PCIe device receivers may be designed to tolerate some dynamic changes in characteristics, and self-adapt (e.g. PLL drift, time eye skew) to deal with small variations around the operating point, if the initial alignment was only marginal or a large shift in electrical characteristics occurs (e.g., due to thermal shock or contamination of the electrical connection) then the BER may be severe enough that there may be no option but to drop speed to a lower speed (e.g. PCIe Gen1/Gen2 speeds) or retrain the PCIe link at the higher speed outside of the initial boot sequence.